FPGA to PCB Training Module Software, documentation and related materials: Copyright © 2006 Altium Limited. All rights reserved. You are permitted to print this document provided that (1) the use of such is for personal use only and will not be copied or posted on any network computer or broadcast in any media, and (2) no modifications of the document is made. Unauthorized duplication, in whole or part, of this document by any means, mechanical or electronic, including translation into another language, except for brief excerpts in published reviews, is prohibited without the express written permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local statute. Violators may be subject to both criminal and civil penalties, including fines and/or imprisonment. Altium, Altium Designer, Board Insight, CAMtastic, CircuitStudio, Design Explorer, DXP, LiveDesign, NanoBoard, NanoTalk, Nexar, nVisage, P-CAD, Protel, SimCode, Situs, TASKING, and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or its subsidiaries. Microsoft, Microsoft Windows and Microsoft Access are registered trademarks of Microsoft Corporation. OrCAD, OrCAD Capture, OrCAD Layout and SPECCTRA are registered trademarks of Cadence Design Systems Inc. AutoCAD is a registered trademark of AutoDesk Inc. HP-GL is a registered trademark of Hewlett Packard Corporation. PostScript is a registered trademark of Adobe Systems, Inc. All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed. Module 7 Altium Designer Training FPGA to PCB FPGA to PCB Training Module 1. From FPGA to PCB....................................................................................................7-1 1.1 1.2 2. 2.1 2.2 2.3 2.4 2.5 3. 3.1 3.2 3.3 3.4 3.5 4. 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 5. 5.1 5.2 5.3 5.4 6. 6.1 6.2 7. 7.1 7.2 7.3 7.4 8. 8.1 8.2 8.3 8.4 9. 9.1 9.2 Introduction ................................................................................................ 7-1 Theory of operation .................................................................................... 7-1 Exercise 1 ­ Simulated accelerometer using a frequency generator............ 7-2 Exercise 2 ­ Simulated accelerometer using DIP-switches ......................... 7-3 Exercise 3 ­ Simulated accelerometer using an IOB................................... 7-3 Exercise 4 ­ Test with real accelerometer................................................... 7-4 Exercise 5 ­ Test with complete software ................................................... 7-5 Which device will fit my design?.................................................................. 7-7 Building for a foreign device........................................................................ 7-8 Flexible configurations .............................................................................. 7-10 Exercise 6 ­ Build for a foreign device ...................................................... 7-11 Exercise 7 ­ Squeezing the design ........................................................... 7-11 Understanding the document stack........................................................... 7-14 Using the FPGA to PCB project wizard ..................................................... 7-16 Choosing the FPGA configuration............................................................. 7-16 Initial FPGA pin assignments.................................................................... 7-17 Choosing the target PCB project............................................................... 7-19 Configuring the FPGA component schematic sheet .................................. 7-19 Configuring the sheet symbol schematic sheet ......................................... 7-20 Exercise 8 ­ Running the FPGA to PCB project wizard............................. 7-21 Modifying the auto generated sheet .......................................................... 7-24 A word about special function FPGA pins ................................................. 7-24 Recreating the autogenerated sheet ......................................................... 7-24 The FPGA workspace map....................................................................... 7-25 The synchronize dialog............................................................................. 7-26 Synchronizing matched signals................................................................. 7-28 Synchronizing unmatched signals............................................................. 7-29 Configuring I/O standards ......................................................................... 7-32 Exercise 9 ­ Using the FPGA signal manager........................................... 7-33 Supported devices.................................................................................... 7-36 Creating the link ....................................................................................... 7-36 Linking an auto generated sheet to an existing PCB project...................... 7-39 Exercise 10 ­ Manually linking a PCB and FPGA project .......................... 7-39 Pin swapping in the PCB document .......................................................... 7-40 Pin swapping in the FPGA project ............................................................ 7-46 Pin swapping in both PCB and FPGA projects .......................................... 7-47 Exercise 11 ­ Pin swapping...................................................................... 7-47 Exercise 12 ­ Migration stage 1................................................................ 7-49 Exercise 13 ­ Migration stage 2................................................................ 7-51 i Enhancing development through component emulation......................................7-2 Migrating to an alternate FPGA device ...................................................................7-7 From FPGA project to PCB project .......................................................................7-14 Maintaining project synchronization.....................................................................7-25 Configuring FPGA I/O .............................................................................................7-32 Manually linking FPGA and PCB projects ............................................................7-35 Pin swapping ...........................................................................................................7-40 Commissioning the design.....................................................................................7-49 Altium Designer Training Module FPGA to PCB 9.3 9.4 9.5 10. Exercise 14 ­ Calibration.......................................................................... 7-51 Exercise 15 ­ Bootstrapping the FPGA..................................................... 7-51 Exercise 16 ­ Reverting to test mode ....................................................... 7-53 Review ......................................................................................................................7-54 7 - ii Altium Designer Training Module FPGA to PCB 1. From FPGA to PCB 1.1 Introduction The NanoBoard is a tremendously powerful embedded platform that can dramatically decrease prototyping efforts and time-to-market. Although some designs may make use of the NanoBoard in the final design, Altium recognize that most designs will need to be transferred from the NanoBoard and onto a custom production board. DXP provides a number of features that assist in the migration of designs to production ready PCBs and this shall be the focus of today's activities. Over the course of today we will take a typical embedded project and follow its development from the working prototype stage through to the fully implemented production PCB. The case study we have chosen is a Digital Spirit Level. 1.2 Theory of operation The digital spirit level contains a MEMS based accelerometer capable of measuring acceleration up to ±2G across two perpendicular axes. Because acceleration due to gravity is known to be a relative constant of 9.8m/s2, we can use trigonometry to calculate the tilt angle of the accelerometer. cos = a / 9.8 therefore: = cos-1(a / 9.8) where a = acceleration experienced by the accelerometer = tilt angle of accelerometer. An accelerometer is most sensitive to tilt when its sensitive axis is perpendicular to the force of gravity, i.e., parallel to the earth's surface. At this orientation its sensitivity to changes in tilt is highest. When the accelerometer is oriented on axis to gravity, i.e., near its +1 g or ­1 g reading, the change in output acceleration per degree of tilt is negligible. When the accelerometer is perpendicular to gravity, its output will change nearly 17.5 mg per degree of tilt, but at 45° degrees it is changing only at 12.2 mg per degree and resolution declines. The 2-axis accelerometer located on the DSL is oriented so that the X and Y axes are in the same plane as the PCB i.e. the X-axis points along the long dimension of the PCB and the Y-axis points along the short dimension. A "bubble" is displayed on the LCD to emulate the operation of a traditional Spirit Level. 9.8 a Figure 1. Accelerometer location on the spirit level PCB. 7-1 Altium Designer Training Module FPGA to PCB 2. Enhancing development through component emulation Often during development it is desirable to begin software development prior to a hardware platform being fully available. This was true when developing this training case study. We had the concept of what it was we wished to build but the accelerometer was some way off being delivered. Rather than delay software development until it arrived, we made use of the flexible FPGA environment to build a simulated accelerometer. By creating a custom piece of hardware that simulated the PWM characteristic of the actual accelerometer, we were able to continue software development and tune our application under very controlled conditions. 2.1 Exercise 1 ­ Simulated accelerometer using a frequency generator To get started quickly, the easiest way to generate an oscillating digital signal is to use a frequency generator. Although this will not give us control over the mark/space ratio, it does allow for control over the period of the signal. A complete project has been created in preparation for this exercise. Your instructor will tell you where to find it on your local hard drive. 1. Open the SpiritLevel.PRJFPG project as directed by your instructor. 2. Observe the contents of the schematic document SL_FPGA_FrqGen.SchDoc. U3 CLK_BRD U4 U6 CLK VCC INIT OR2N1S GND Reset CLK RST EA SFRDATAO[7..0] SFRDATAI[7..0] SFRADDR[6..0] SFRWR SFRRD P0O[7..0] P0I[7..0] P1O[7..0] P1I[7..0] P2O[7..0] P2I[7..0] P3O[7..0] P3I[7..0] DELAY[7..0] FPGA_STARTUP8 U1 CLK DIN[7..0] DOUT[7..0] ADDR[11..0] WE [11..0] U9 FREQ INV [11..0] RAMS_8x4K U7 TIMEBASE ROMDATAO[7..0] ROMDATAI[7..0] MEMDATAO[7..0] MEMDATAI[7..0] ROMADDR[15..0] ROMWR MEMADDR[15..0] ROMRD MEMWR MEMRD INT0 PSWR INT1 PSRD T0 T1 Frequency Generator CLKGEN GND RXD TXD RXDO TSK51A OCD Microprocessor TSK51A_D Figure 2. Using a frequency generator to simulate an accelerometer input 3. Build the design and download it to the NanoBoard. 4. Set the NanoBoard Clock to 50MHz and the frequency generator to 1Khz. 5. Observe the output on the LCD. The bottom row of the LCD should show two variables being updated; T1 and T2. These are the calculations made by the timer routine for the corresponding T1 and T2 time intervals defined on the accelerometer datasheet. 7-2 Altium Designer Training Module FPGA to PCB 6. Set the frequency of the clock generator to a value around 1KHz. Because we are sending a 50% duty cycle signal to the processor, T2 should be almost exactly double T1. 7. Save your work. It will be used for the basis of the next couple of exercises. 2.2 Exercise 2 ­ Simulated accelerometer using DIP-switches The next step will make use of the PWM circuit developed in Exercise 1 of Day 1. This circuit operates at a fixed frequency but now we have control over the mark / space ratio. 1. Before doing any modifications, save SL_FPGA_FrqGen.SchDoc as SL_FPGA_PWM.SchDoc. 2. Modify SL_FPGA_PWM.SchDoc to include the PWM circuit instead of the Frequency Generator as shown in Figure 3. U3 P182 P3 CLK_BRD TEST_BUTTON CLK_BRD U4 U6 CLK VCC INIT OR2N1S GND Reset CLK RST EA SFRDATAO[7..0] SFRDATAI[7..0] SFRADDR[6..0] SFRWR SFRRD P0O[7..0] P0I[7..0] P1O[7..0] P1I[7..0] P2O[7..0] P2I[7..0] DELAY[7..0] FPGA_STARTUP8 U1 CLK DIN[7..0] DOUT[7..0] ADDR[11..0] WE [11..0] U9 INV GT LT GND [11..0] RAMS_8x4K U7 VCC U12 CB8CEB Q[7..0] U8 A[7..0] B[7..0] COMPM8B P3O[7..0] P3I[7..0] ROMDATAO[7..0] ROMDATAI[7..0] MEMDATAO[7..0] MEMDATAI[7..0] ROMADD ...